WEBVTT 00:00.440 --> 00:01.280 Hello everyone. 00:01.320 --> 00:03.200 I'm Typhoon and welcome to this lecture. 00:03.200 --> 00:08.520 In this lecture, we will dive deep into one of the most fundamental and powerful innovations in digital 00:08.520 --> 00:10.520 electronics, which is C. 00:11.080 --> 00:22.200 Or you may ask what this means is CMOs stands for complementary metal oxide semiconductor. 00:22.440 --> 00:29.640 This elegant design principle lies at the heart of almost every modern logic circuit, from your computer's 00:29.680 --> 00:33.400 CPU to the microcontroller inside a smartwatch. 00:34.680 --> 00:40.760 This is a more smarter way to switch, and in earlier digital logic designs, we relied on resistors 00:40.760 --> 00:43.120 for pull up and pull down operations. 00:43.120 --> 00:46.240 While this worked, it has significant limitations. 00:46.240 --> 00:53.000 As learned and then explained in our previous lectures, it consumed continuous power even when the 00:53.000 --> 00:57.440 signal wasn't switching, and it was relatively slow due to the passive nature of resistors. 00:57.720 --> 01:02.990 And this is where the cosmos comes in as a game changer. 01:03.030 --> 01:04.710 The CMOs technology. 01:04.710 --> 01:12.350 Complementary metal oxide semiconductor circuits use two complementary types of transistors a p-channel 01:12.350 --> 01:26.430 mOSFET, also called PMOs, which conducts when the input is low, and an n-channel mOSFET or an M or 01:26.550 --> 01:29.790 S, which conducts when the input is high. 01:30.190 --> 01:35.830 You have learned P-channel and n-channel mOSFET in previous lectures, so I. 01:36.110 --> 01:42.550 If you didn't watch the previous lecture, I highly, highly recommend you watch this course's lectures 01:42.550 --> 01:43.630 one by one. 01:43.630 --> 01:47.710 And do not skip any lectures between lectures here. 01:48.790 --> 01:56.590 And yeah, you need to learn about mOSFET and p-channel MOSFETs and n-channel mOSFET in order to understand 01:56.590 --> 01:59.420 this CMOs concept at all. 02:00.180 --> 02:08.420 So by pairing this together and connecting their drains like that, you can see we have connected their 02:08.460 --> 02:09.100 drains. 02:11.300 --> 02:14.220 We form basically a CMOs inverter. 02:15.620 --> 02:21.420 This simple yet powerful arrangement is the building block for countless digital circuits. 02:21.860 --> 02:27.420 So here in this, uh, here I have created a CMOs inverter. 02:28.020 --> 02:33.300 Um, now at the top of the circuit we see a p-channel mOSFET. 02:33.660 --> 02:36.620 It is it's actually use a different color. 02:36.780 --> 02:43.420 So yeah, at the bottom of the circuit, uh, we are seeing the p-channel mOSFET. 02:43.620 --> 02:53.820 Its source terminal is connected to five volts, which we treat this logic one or binary one, logic 02:53.820 --> 02:55.020 II or binary one. 02:55.020 --> 02:55.130 91. 02:55.850 --> 03:03.410 And at the bottom here we see an n channel mOSFET. 03:03.890 --> 03:11.210 And now its source is connected to zero volts representing the logic low or binary zero. 03:11.770 --> 03:22.170 And we also have the gate terminals of both transistors are tied together like this and used as the 03:22.170 --> 03:28.250 input to the inverter and the drain terminals of the. 03:28.250 --> 03:34.170 Both MOSFETs are also connected together, forming the output of the inverter. 03:34.610 --> 03:40.970 Now this symmetrical design allows one transistor to be on while the other is off depending the input 03:40.970 --> 03:41.490 voltage. 03:41.490 --> 03:47.770 Now, this mutual exclusivity is what makes CMOs so power efficient and responsive. 03:48.730 --> 03:56.150 So let's now examine how the circuit behaves under different input conditions Which shows two cases 03:56.150 --> 03:56.510 here. 03:56.950 --> 04:00.990 In the case, one input voltage of the input voltage is five volts. 04:00.990 --> 04:04.510 The input gate is at five volts. 04:05.030 --> 04:16.230 Now this turns off the P-channel mOSFET because p MOSFETs require low voltage low voltage to conduct 04:17.350 --> 04:21.910 here, and the N-channel mOSFET turns on here. 04:23.230 --> 04:31.430 Now the output is connected to zero volts through the n mOSFET, so n channel turns on because it is 04:31.470 --> 04:34.230 activated by a high voltage. 04:35.350 --> 04:36.710 So the output is pulled. 04:36.710 --> 04:41.990 Now is low so it is zero volts. 04:42.990 --> 04:52.940 And in the case two, if the input gate here is zero volts, what we will get basically is the p-channel 04:52.940 --> 05:04.660 mOSFET turns on, and now a low gate voltage allows it to conduct, and the n-channel mOSFET turns off 05:05.380 --> 05:08.180 as it needs high voltage to conduct. 05:09.020 --> 05:10.260 This makes sense, right? 05:10.860 --> 05:15.740 So with the p-channel conducting, the output is connected. 05:15.980 --> 05:17.580 To what. 05:17.620 --> 05:20.420 Where to five volts. 05:21.500 --> 05:24.620 So basically the output is pulled high. 05:24.940 --> 05:26.420 Let me fix my microphone here. 05:26.460 --> 05:26.940 Yeah. 05:27.060 --> 05:33.620 So the output is pulled high which is basically five volts in our this diagram. 05:34.820 --> 05:44.260 And yeah now if we summarize this logic with the table what we will get basically is we have the gates. 05:45.300 --> 05:49.140 As you know the gates is basically the input of our transistors. 05:50.130 --> 05:54.170 And we also have the output or drains. 05:54.210 --> 05:57.810 That's actually first drains which is output. 05:58.650 --> 06:06.370 So here in the input, if we give the zero volts which is low in the output we will get five volts. 06:06.810 --> 06:10.090 If we give five volts we will get zero volts. 06:10.090 --> 06:16.290 So the output is basically always opposite of the input like a logic node. 06:17.210 --> 06:23.290 And we can also use the CMOs and gate using inverters. 06:23.730 --> 06:30.050 Now let's move beyond inverter and analyze the CMOs and and gate. 06:31.090 --> 06:45.050 Um so here in this diagram I'm basically uh demonstrating how we can construct an and gate using three 06:45.410 --> 06:48.570 CMOs logic stages.